An analog-to digital converter (ADC) typically comprises, for each channel to be sampled, an input switch, and a sampling capacitor onto which the signal to be converted is sampled via the switch. In order to limit the amount of noise in the sampled signal it is usual to include a band-limiting RC filter at the input of the ADC channel between the input node and the input switch. Ideally, the bandwidth of the RC filter would match that of the desired signal being sampled, but in practice this has not proven to be possible whilst also allowing acceptably short settling times for the ADC. This is because the components of the ADC introduce various non-linear parasitic capacitances, particularly in the back gates of the input switch, which require charging sufficiently to allow for stable signal acquisition.
In order to allow for sufficiently quick ADC operation given the finite charge time of these parasitic capacitances, a broader bandwidth RC filter must be employed, to allow charge to pass quickly enough to the parasitic capacitances from the input node to allow them to settle quickly enough for the desired sampling rate. For example, in one known ADC available from the present Applicant (the LTC2387-18), a RC filter bandwidth of 77 MHz is required in order to sample a 50 kHz signal. This large bandwidth significantly increases the sampled noise, which in many cases leads to high power dissipation in the ADC drive circuitry.